Functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied

ABSTRACT

Object The present invention relates to a to-be-mounted electronic component to which functional alloy plating using a bonding material for mounting is applied with a substitute bonding material for solder (tin-lead alloy), and aims at providing alloy plating which has been put to a practical use in such a way that the function of existing alloy plating of this type has been significantly improved to eliminate toxic plating from various kinds of electronic components for use in electronic devices so that it is useful in protecting the environment.  
     Construction  
     Functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that with Sn (tin) as a base, one of Bi (bismuth), Ag (silver) and Cu (copper) is selected, a Bi content to the Sn is set to 1.0% or less, the Bi content to the Sn is set to 2.0 to 10.0%, an Ag content to the Sn is set to 1.0 to 3.0%, the Ag content to the Sn is set to 3.0 to 5.0%, the Ag content to the Sn is set to 8.0 to 10.0%, or a Cu content to the Sn is set to 0.5 to 1.0%, and an electrolytic process is performed with a special waveform.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application is a divisional application of U.S.application Ser. No. 09/566,125 filed May 5, 2000, and which claimspriority of Japanese Application No. 11-164307, filed May 7, 1999. Theentire disclosure of application Ser. No. 09/566,125 is considered asbeing part of the disclosure of this application, and the entiredisclosure of application Ser. No. 09/566,125 is expressly incorporatedby reference herein in its entirety.

DETAILED DESCRIPTION OF THE INVENTION Field of Utilization in Industry

[0002] The present invention relates to a to-be-mounted electroniccomponent to which functional alloy plating using a bonding material formounting is applied with a substitute bonding material for solder(tin-lead alloy), and aims at providing alloy plating which has been putto a practical use in such a way that the function of existing alloyplating of this type has been significantly improved to eliminate toxicplating from various kinds of electronic components for use inelectronic devices so that it is useful in protecting the environment.

Background of the Invention

[0003] As solder which does not use lead (Pb) (Pb-free solder), variousnew bonding agents have been developed and their properties becomeapparent. And, the stage is proceeding to the development of theirmanufacturing methods. Tin (Sn)-bismuth (Bi), Sn-indium alloy (In),Sn-zinc alloy (Zn), Sn plating etc. are considered as Pb-free solder todevices. The cost for the Sn—In alloy among them is extremely high,about 25 times the cost for Sn—Bi. The Sn—Zn alloy has a problem on thesolderability after heat resistance because Zn is prone to be oxidized.This leaves Sn—Ag, Sn—Bi and Sn.

[0004] Bi on copper may be thermally diffused at the time of reflow andmay be peeled, so that Sn—Bi for devices should have nickel applied as abase in order to avoid the peeling.

[0005] If a coat offset (melt-originated offset) occurs when asurface-mounting device is melted, the bonding surface has a roughsurface, so that the bonding surface becomes smaller, thus lowering thebonding strength. Prevention of a melt-originated offset which makesorganic eutectoid in a coat extremely small is attempted by applyingplating according to this invention.

Prior Art

[0006] Conventionally, solder (tin-lead alloy) has been used for a longtime as a bonding material for mounting electronic device components.Recently, the harmfulness of lead has been noticed mainly in America andEurope and removal of lead from electronic devices has progressedrapidly.

[0007] Meanwhile, in Japan has already started a movement of voluntaryremoval mainly by the electronics industry.

[0008] Electroplating is applied to most of materials for to-be-mountedelectronic components as tinning. Therefore, there is a pressing need toindustrialize plating of substitute alloys for the industrial growth.

Problem to be Solved by the Invention

[0009] As solder which is an essential bonding material for theaforementioned electronic components contain lead (Pb), however, whenelectronic devices are disposed of, lead would be melted and seep intogroundwater from a junk yard, raising a problem of environmentalpollution, unless electronic components having to-be-mounted partscontaining solder's lead are removed.

Means for Solving the Problem

[0010] Accordingly, it is an object of this invention to overcome theproblem of the prior art and to provide electronic components to be onwhich very practical alloy plating for bonding that is the existingalloy plating of this type which has been improved significantly isapplied using a substitute metal for lead in solder alloy plating.

[0011] The first of this invention is functional alloy plating usingsubstitute bonding material for Pb and electronic component to bemounted to which the functional alloy plating is applied, characterizedin that with Sn as a base, one of Bi, Ag and Cu is selected, a Bicontent to the Sn is set to 1.0% or less, the Bi content to the Sn isset to 2.0 to 10.0%, an Ag content to the Sn is set to 1.0 to 3.0%, theAg content to the Sn is set to 3.0 to 5.0%, the Ag content to the Sn isset to 8.0 to 10.0%, or a Cu content to the Sn is set to 0.5 to 1.0%,and an electrolytic process is performed with a special waveform.

[0012] The second of this invention is functional alloy plating usingsubstitute bonding material for Pb and electronic component to bemounted to which the functional alloy plating is applied, characterizedin that an IC chip is wire-bonded to a lead frame and outer leadsexposed outside a molded IC package are subjected to an electrolyticprocess with a Bi content to Sn whose content is 99.0% or greater beingset to 1.0% or less and with a special waveform.

[0013] The third of this invention is functional alloy plating usingsubstitute bonding material for Pb and electronic component to bemounted to which the functional alloy plating is applied, characterizedin that an IC chip is wire-bonded to a lead frame and outer leadsexposed outside a molded IC package are subjected to an electrolyticprocess with a Bi content to Sn whose content is 98.0 to 90.0% being setto 2.0 to 10.0% and with a special waveform.

[0014] The fourth of this invention is functional alloy plating usingsubstitute bonding material for Pb and electronic component to bemounted to which the functional alloy plating is applied, characterizedin that an IC chip is wire-bonded to a lead frame and outer leadsexposed outside a molded IC package are subjected to an electrolyticprocess with an Ag content to Sn whose content is 99.0 to 97.0% beingset to 1.0 to 3.0% and with a special waveform.

[0015] The fifth of this invention is functional alloy plating usingsubstitute bonding material for Pb and electronic component to bemounted to which the functional alloy plating is applied, characterizedin that an IC chip is wire-bonded to a lead frame and outer leadsexposed outside a molded IC package are subjected to an electrolyticprocess with an Ag content to Sn whose content is 97.0 to 95.0% beingset to 3.0 to 5.0% and with a special waveform.

[0016] The sixth of this invention is functional alloy plating usingsubstitute bonding material for Pb and electronic component to bemounted to which the functional alloy plating is applied, characterizedin that an IC chip is wire-bonded to a lead frame and outer leadsexposed outside a molded IC package are subjected to an electrolyticprocess with an Ag content to Sn whose content is 92.0 to 90.0% beingset to 8.0 to 10.0% and with a special waveform.

[0017] The seventh of this invention is functional alloy plating usingsubstitute bonding material for Pb and electronic component to bemounted to which the functional alloy plating is applied, characterizedin that an IC chip is wire-bonded to a lead frame and outer leadsexposed outside a molded IC package are subjected to an electrolyticprocess with a Cu content to Sn whose content is 99.5 to 99.0% being setto 0.5 to 1.0% and with a special waveform.

[0018] The eighth of this invention is functional alloy plating usingsubstitute bonding material for Pb and electronic component to bemounted to which the functional alloy plating is applied, characterizedin that an electrode pattern of a printed circuit board is subjected toan electrolytic process with a Bi content to Sn whose content is 99.0%or greater being set to 1.0% or less and with a special waveform.

[0019] The ninth of this invention is functional alloy plating usingsubstitute bonding material for Pb and electronic component to bemounted to which the functional alloy plating is applied, characterizedin that an electrode pattern of a printed circuit board is subjected toan electrolytic process with a Bi content to Sn whose content is 98.0 to90.0% being set to 2.0 to 10.0% and with a special waveform.

[0020] The tenth of this invention is functional alloy plating usingsubstitute bonding material for Pb and electronic component to bemounted to which the functional alloy plating is applied, characterizedin that an electrode pattern of a printed circuit board is subjected toan electrolytic process with an Ag content to Sn whose content is 99.0to 97.0% being set to 1.0 to 3.0% and with a special waveform.

[0021] The eleventh of this invention is functional alloy plating usingsubstitute bonding material for Pb and electronic component to bemounted to which the functional alloy plating is applied, characterizedin that an electrode pattern of a printed circuit board is subjected toan electrolytic process with an Ag content to a content of 97.0 to 95.0%being set to 3.0 to 5.0% and with a special waveform.

[0022] The twelfth of this invention is functional alloy plating usingsubstitute bonding material for Pb and electronic component to bemounted to which the functional alloy plating is applied, characterizedin that an electrode pattern of a printed circuit board is subjected toan electrolytic process with an Ag content to a content of 92.0 to 90.0%being set to 8.0 to 10.0% and with a special waveform.

[0023] The thirteenth of this invention is functional alloy platingusing substitute bonding material for Pb and electronic component to bemounted to which the functional alloy plating is applied, characterizedin that an electrode pattern of a printed circuit board is subjected toan electrolytic process with a Cu content to Sn whose content is 99.5 to99.0% being set to 0.5 to 1.0% and with a special waveform.

[0024] The fourteenth of this invention is functional alloy platingusing substitute bonding material for Pb and electronic component to bemounted to which the functional alloy plating is applied, characterizedin that a chip tantalum capacitor is wire-bonded to a lead frame andouter leads exposed outside the chip tantalum capacitor are subjected toan electrolytic process with a Bi content to Sn whose content is 99.0%or greater being set to 1.0% or less and with a special waveform.

[0025] The fifteenth of this invention is functional alloy plating usingsubstitute bonding material for Pb and electronic component to bemounted to which the functional alloy plating is applied, characterizedin that a chip tantalum capacitor is wire-bonded to a lead frame andouter leads exposed outside the chip tantalum capacitor are subjected toan electrolytic process with a Bi content to Sn whose content is 98.0 to90.0% being set to 2.0 to 10.0% and with a special waveform.

[0026] The sixteenth of this invention is functional alloy plating usingsubstitute bonding material for Pb and electronic component to bemounted to which the functional alloy plating is applied, characterizedin that a chip tantalum capacitor is wire-bonded to a lead frame andouter leads exposed outside the chip tantalum capacitor are subjected toan electrolytic process with an Ag content to Sn whose content is 99.0to 97.0% being set to 1.0 to 3.0% and with a special waveform.

[0027] The seventeenth of this invention is functional alloy platingusing substitute bonding material for Pb and electronic component to bemounted to which the functional alloy plating is applied, characterizedin that a chip tantalum capacitor is wire-bonded to a lead frame andouter leads exposed outside the chip tantalum capacitor are subjected toan electrolytic process with an Ag content to Sn whose content is 97.0to 95.0% being set to 3.0 to 5.0% and with a special waveform.

[0028] The eighteenth of this invention is functional alloy platingusing substitute bonding material for Pb and electronic component to bemounted to which the functional alloy plating is applied, characterizedin that a chip tantalum capacitor is wire-bonded to a lead frame andouter leads exposed outside the chip tantalum capacitor are subjected toan electrolytic process with an Ag content to Sn whose content is 92.0to 90.0% being set to 8.0 to 10.0% and with a special waveform.

[0029] The nineteenth of this invention is functional alloy platingusing substitute bonding material for Pb and electronic component to bemounted to which the functional alloy plating is applied, characterizedin that a chip tantalum capacitor is wire-bonded to a lead frame andouter leads exposed outside the chip tantalum capacitor are subjected toan electrolytic process with a Cu content to Sn whose content is 99.5 to99.0% being set to 0.5 to 1.0% and with a special waveform.

[0030] The twentieth of this invention is functional alloy plating usingsubstitute bonding material for Pb and electronic component to bemounted to which the functional alloy plating is applied, characterizedin that general electronic device component materials including acomponent material which needs plating for bonding and a generalcomponent material which needs plating as a functional component aresubjected to an electrolytic process with a Bi content to Sn whosecontent is 99.0% or greater being set to 1.0% or less and with a specialwaveform.

[0031] The twenty-first of this invention is functional alloy platingusing substitute bonding material for Pb and electronic component to bemounted to which the functional alloy plating is applied, characterizedin that general electronic device component materials including acomponent material which needs plating for bonding and a generalcomponent material which needs plating as a functional component aresubjected to an electrolytic process with a Bi content to Sn whosecontent is 98.0 to 90.0% being set to 2.0 to 10.0% and with a specialwaveform.

[0032] The twenty-second of this invention is functional alloy platingusing substitute bonding material for Pb and electronic component to bemounted to which the functional alloy plating is applied, characterizedin that general electronic device component materials including acomponent material which needs plating for bonding and a generalcomponent material which needs plating as a functional component aresubjected to an electrolytic process with an Ag content to Sn whosecontent is 99.0 to 97.0% being set to 1.0 to 3.0% and with a specialwaveform.

[0033] The twenty-third of this invention is functional alloy platingusing substitute bonding material for Pb and electronic component to bemounted to which the functional alloy plating is applied, characterizedin that general electronic device component materials including acomponent material which needs plating for bonding and a generalcomponent material which needs plating as a functional component aresubjected to an electrolytic process with an Ag content to Sn whosecontent is 97.0 to 95.0% being set to 3.0 to 5.0% and with a specialwaveform.

[0034] The twenty-fourth of this invention is functional alloy platingusing substitute bonding material for Pb and electronic component to bemounted to which the functional alloy plating is applied, characterizedin that general electronic device component materials including acomponent material which needs plating for bonding and a generalcomponent material which needs plating as a functional component aresubjected to an electrolytic process with an Ag content to Sn whosecontent is 92.0 to 90.0% being set to 8.0 to 10.0% and with a specialwaveform.

[0035] The twenty-fifth of this invention is functional alloy platingusing substitute bonding material for Pb and electronic component to bemounted to which the functional alloy plating is applied, characterizedin that general electronic device component materials including acomponent material which needs plating for bonding and a generalcomponent material which needs plating as a functional component aresubjected to an electrolytic process with a Cu content to Sn whosecontent is 99.5 to 99.0% being set to 0.5 to 1.0% and with a specialwaveform.

EMBODIMENT Significance of Special Waveform

[0036] A description will now be given of the aforementioned“electrolytic process with a special waveform”. First, typicalelectroplating is DC plating, i.e., plating with a voltage having an ACvoltage rectified by a rectifier.

[0037] To perform plating, it is necessary to combine and add severaltypes of organic additives into a plating solution so that the crystalgrain size of metal to be deposited does not become resin particle size.

[0038] Of course, those organic materials become eutectoid at the sametime as the metal to be plated, causing many defects on their functionsas bonding materials.

[0039] The “electrolytic process with a special waveform” in thisinvention improves those shortcomings, and an additive to be added intoa plating solution is only a slight amount of a surface active agentwhich is not decomposed and disposed, and this special waveform servesas an organic additive.

[0040] In this invention, the special waveform is a pulse waveform whichis acquired for an electrolytic process from a current that has beenrectified with a thyristor 6-phase half wave. Thus, the electrolyticprocess uses a pulse waveform which can cycle between positive andnegative.

[0041] The following shows a table of the types of mass-producibleplatings. TABLE 1 Melt- originated Coats Composition offset Note Sn-AgAg 10% special ◯ Plating by special waveform plating waveform method ofthis invention Sn-Ag Ag 3% special X Melt-originated offset waveformplating present even with plating by special waveform method of thisinvention Sn-Bi Bi 3% special ◯ Plating by special waveform platingwaveform method of this invention Sn Sn 100% X Normal gloss plating SnSn 99% special ◯ Plating by special waveform plating waveform method ofthis invention Sn-Pb Pb 10% special ◯ Plating to which waveform platingexisting chip tantlum is applied

[0042] As there are different coat characteristics to be acquireddepending on whether the lead types of devices to be used are leadlines, a lead frame or leadless, they should be selectively used, butthe added values of the devices differ device by device so that acost-based selection is also considered as an important factor.

[0043] In the comparison of the costs for plating materials, the costfor the base acid is high even if an inexpensive metal is used, so thatthe cost does not decrease as indicated in the comparison of the pricesof metals. A further variation is seen when it is run as plating.

[0044] Then, the following table shows the evaluation of Pb-free coatsas coats. TABLE 2 Types of coats Contents Note Sn-Ag plating Ag 3-10%Melting point of 220-260° C. Melt-originated offset occurred by C, Agcomposition. Glossy appearance Sn-bi plating special waveform Meltingpoint of 220-225° C. plating contain- Fragile due to diffusion of ing Biof 2-5% Bi into C, copper base. Glossless appearance Sn platingDifferent type Melting point of 225-230° C. of metal of 0.2- Goodreflow. Semi-gloss 1% contained as appearance additive

[0045] The following table shows a list of the evaluation of theindividual coats. TABLE 3 Sn-Ag Sn-Bi Sn Appearance Gloss GlosslessSemi-gloss Plating 4.03 μm 4.21 μm 3.99 μm thickness Composition Sn92.46% Sn 97.31% Sn 99.84% Ag 7.54% Bi 2.69% Bi 0.16% Heat DiscolorationPassed Passed resistance present Solderability Passed Passed Passedafter heat resistance Bending after Passed Passed Passed heat resistancePeeling after Passed Passed Passed heat resistance Melt- Present NoneNone originated offset Solder Zero-cross Zero-cross Zero-crosswettability 0.65 sec 0.85 sec 0.50 sec before heat Wet strength Wetstrength Wet strength resistance 71.4 mg 23.0 mg 31.4 mg SolderZero-cross Zero-cross Zero-cross wettability 0.95 sec 0.87 sec 0.61 secafter heat Wet strength Wet strength Wet strength resistance 26.4 mg23.0 mg 34.2 mg Bonding 0.37 Kg before 1.56 Kg before 1.63 Kg beforestrength heat heat heat resistance resistance resistance 0.05 Kg after0.05 Kg after 0.70 Kg after heat heat heat resistance resistanceresistance Vickers 16.3 23.0 11.4 hardness

[0046] The following table shows the costs for the individual coats.TABLE 4 Price of Price in mass- Sample price prototype production (¥/Kg)(¥/Kg) (¥/Kg) Sn-Ag 2,352 2,114 1,685 Sn-Bi 1,488 1,363 1,148 Sn specialwave- 1,518 1,518 1,089 form plating Special wave- — — — form plating

[0047] While the samples shown above had a nickel (Ni) base to avoiddiffusion on copper, Sn—Ag showed such a phenomenon that oxidization onNi through Ag at the time of heat resistance lowered the bondability. Inthis respect, it is contemplated that copper (Cu) is suitable as thebase for Sn—Ag. Further, heat-resistance-originated discoloration andmelt-originated offset also occurred. To cope with this melt-originatedoffset, it is necessary to obtain Sn—Ag plating containing 85% or moreof Ag, which is naturally a factor to increase the cost. Slightsegregation is seen on the surface of Sn—Bi. Sn—Ag and Sn-specialwaveform plating still suffer poor solution efficiencies and the linespeeds remain about a half the speed of the current special-waveformplating. Although solution conditions were so set as to provide theoptimal appearance in the implementation of the scheme, improvements canbe made on the density of the solution, the density of the additive,stirring and so forth. In the case of surface mounting, there may be aquestion on the behavior of Bi, such as segregation or diffusion. Inthis respect, Bi in the Sn-special waveform plating has a minute amountand serves to adjust the deposition of the plated coat so that it doesnot seem to raise a problem on segregation or diffusion.

[0048] The following gives the results of the evaluation of samples ofSn—Ag, Sn—Bi and Sn plating to chip tantalum frames. (1) PlatingSpecifications base plating Ni 0.5 to 1.0 μm (same for all) finishingplating Sn-Ag 3.0 to 5.0 μm Sn-Bi 3.0 to 5.0 μm Sn 3.0 to 5.0 μm

[0049] (2) Test Results

“Sn—Ag”

[0050] a. Appearance: passed (free of spot, stain and discoloration)

[0051] b. Heat resistance: discoloration present (160° C.×6 Hr heatresistance. no expansion, peeling, discoloration and fall-off)

[0052] c. Solderability test: passed (after heat resistance, 230° C.×3sec×once n=1)

[0053] d. Bending test: passed (after heat resistance, 180° C.,bend-back test, measured at A n=1)

[0054] e. Melt-originated: no melt-originated offset (no heat offsetresistance 270° C.×30 min×once n=1)

[0055] f. Peeling test: passed (sample before and after heat resistancen=1)

[0056] g. Melting point: 222° C.

[0057] h. Hardness (Vickers hardness): 16.3

[0058] i. Solder: zero-cross time before heat resistance wettabilityaverage 0.65 (sec) after heat resistance average 0.95 (sec)

[0059] : wet strength before heat resistance average 71.40 (mg) afterheat resistance average 26.40 (mg) (n=5)

[0060] j. Bonding: before heat resistance average 0.37 (kg) strength:after heat resistance average 0.05 (kg) (n=5)

[0061] k. Plating thickness: average 4.03 (μm) (measured withfluorescent X rays n=9)

[0062] l. Composition: Sn 92.46%

[0063] : Ag 7.54%

“Sn—Bi”

[0064] a. Appearance: passed (free of spot, stain and discoloration)

[0065] b. Heat resistance: passed (160° C.×6 Hr heat resistance. noexpansion, peeling, discoloration and fall-off)

[0066] c. Solderability test: passed (after heat resistance, 230° C.×3sec×once n=1)

[0067] d. Bending test: passed (after heat resistance, 180° C.,bend-back test, measured at A n=1)

[0068] e. Melt-originated: no melt-originated offset (no heat offsetresistance 270° C.×30 min×once n=1)

[0069] f. Peeling test: passed (sample before and after heat resistancen=1)

[0070] g. Melting point: 228° C.

[0071] h. Hardness (Vickers hardness): 23.0

[0072] i. Solder: zero-cross time before heat resistance wettabilityaverage 0.85 (sec) after heat resistance average 0.87 (sec)

[0073] : wet strength before heat resistance average 23.0 (mg) afterheat resistance average 23.0 (mg) (n=5)

[0074] j. Bonding : before heat resistance average 1.56 (kg) strength:after heat resistance average 0.56 (kg) (n=5)

[0075] k. Plating thickness: average 4.21 (μm) (measured withfluorescent X rays n=9)

[0076] l. Composition: Sn 97.31%

[0077] : Bi 2.69% (measured at A)

“Sn”

[0078] a. Appearance: passed (free of spot, stain and discoloration)

[0079] b. Heat resistance: discoloration present (160° C.×6 Hr heatresistance. no expansion, peeling, discoloration and fall-off)

[0080] c. Solderability test: passed (after heat resistance, 230° C.×3sec×once n=1)

[0081] d. Bending test: (after heat resistance, 180° C., bend-back test,measured at A n=1)

[0082] e. Melt-originated: no melt-originated offset (no heat offsetresistance 270° C.×30 min×once n=1)

[0083] f. Peeling test: passed (sample before and after heat resistancen=1)

[0084] g. Melting point: 232° C.

[0085] h. Hardness (Vickers hardness): 11.40° C.

[0086] i. Solder : zero-cross time before heat resistance wettabilityaverage 0.50 (sec) after heat resistance average 0.61 (sec)

[0087] : wet strength before heat resistance average 31.40 (mg) afterheat resistance average 34.20 (mg) (n=5)

[0088] j. Bonding: before heat resistance average 1.63 (kg) strength:after heat resistance average 0.70 (kg) (n=5)

[0089] k. Plating thickness: average 3.99 (μm) (measured withfluorescent X rays n=9)

[0090] l. Composition: Sn 99.84%

[0091] : Bi 0.16% (measured at A)

[0092] (3) Evaluation Method and Data

[0093] {circle over (1)} Hardness (Vickers hardness) measuringconditions Measure portion “A” of non-heat-resisted samples under thefollowing conditions by using a super light load minute hardness meter(model mvk-1).

[0094] a. load : 0.5 fg

[0095] b. load keeping time: 15 sec

[0096] c. load speed : 0.01 mm/sec

[0097] Measure the diagonal line of a dent three times and compute theVickers hardness from the average dent area.

[0098] {circle over (2)} Zero-crossing time, wet strength measuringconditions

[0099] Five portions “A” of samples S of a frame were sampled from onepiece shown in FIG. 1 and were measured under the following conditionsusing a solder checker (SAT-2000).

[0100] a. Sn 60%, Pb 40%

[0101] b. TEMP 230° C., SPEED 25 mm/sec

[0102] c. DEPTH 2 m, SENS 1

[0103] d. Flux present (MI L type R used)

[0104] (4) Solder Wettability Data

[0105] {circle over (1)} The solder wettability data of Sn—Ag isillustrated in Table 5. TABLE 5 Sn-Ag Data Average Zero-cross before0.65 0.69 0.63 0.67 0.60 0.65 heat resistance (sec) after heat 1.02 0.900.80 1.00 1.05 0.95 resistance Wet strength before 84.0 69.0 81.0 55.068.0 71.4 heat resistance (mg) after heat 32.0 23.0 27.0 20.0 30.0 26.4resistance

[0106] {circle over (2)} The solder wettability data of Sn—Bi isillustrated in Table 6. TABLE 6 Sn-Bi Data Average Zero-cross before1.01 0.82 0.97 0.62 0.83 0.85 heat resistance (sec) after heat 0.76 0.850.99 0.89 0.88 0.87 resistance Wet strength before 16.0 24.0 19.0 35.021.0 23.0 heat resistance (mg) after heat 25.0 22.0 24.0 20.0 24.0 23.0resistance

[0107] {circle over (3)} The solder wettability data of Sn isillustrated in Table 7. TABLE 7 Sn Data Average Zero-cross before 0.490.49 0.34 0.54 0.64 0.50 heat resistance (sec) after heat 0.73 0.49 0.610.59 0.63 0.61 resistance Wet strength before 27.0 34.0 44.0 28.0 24.031.4 heat resistance (mg) after heat 28.0 41.0 32.0 37.0 33.0 34.2resistance

[0108] (5) Bonding Strength Measuring Conditions

[0109] Cut portion “C” under leads at 3 mm in width, and sample ten fromtwo pieces. Place cut samples one on another with a clearance of 0.3 mmand solder-dip under the following conditions using a solder checker.

[0110] a. Sn 60%, Pb 40%

[0111] b. TEMP 230° C., SPEED 25 mm/sec

[0112] c. DEPTH 2 mm, SENS 1

[0113] d. Flux present (MI L type R used)

[0114] Measure the force to peeling by using a push-pull gauge. TABLE 8Sn-Ag Data Average Sample before heat 0.38 0.29 0.53 0.37 0.28 0.37resistance Sample after heat 0.03 0.07 0.08 0.02 0.05 0.05 resistance

[0115] TABLE 9 Sn-Bi Data Average Sample before heat 1.30 1.54 1.23 1.522.21 1.56 resistance Sample after heat 0.53 0.35 0.74 0.54 0.65 0.56resistance

[0116] TABLE 10 Sn-Bi Data Average Sample before heat 1.32 1.82 1.621.57 1.83 1.63 resistance Sample after heat 0.57 0.62 0.60 1.01 0.690.70 resistance

[0117] (6) Plating Thickness Measuring Portion

[0118] Three portions “A”, “a” and “b” of a sample S of a frame perpiece were measured and as there were five pieces of frames, a total ofnine portions, both ends and the center, were measured using fluorescentX rays. TABLE 11 Left end Average Sn-Ag of frame Center Right end (μm)Measuring 3.99 4.04 4.10 portion A a 3.85 3.97 4.05 b 4.07 4.21 4.034.03

[0119] TABLE 12 Left end Average Sn-Bi of frame Center Right end (μm)Measuring 4.29 3.95 3.75 portion A a 4.08 4.31 4.27 b 4.47 4.54 4.214.21

[0120] TABLE 13 Left end Average Sn-Ag of frame Center Right end (μm)Measuring 4.53 3.79 3.70 portion A B 4.27 3.83 3.95 C 3.99 3.94 3.893.99

[0121] (7) Measuring Portions

[0122] As shown in FIG. 1, the measuring portions “A” and “B” of thesample S of the frame may indicate other portions of the same shapes inone piece. That is, it means that they include the measuring portion “A”and portions “a” and “b” or the like.

[0123] With regard to the evaluation coats, evaluation method andmeasuring method, the results of the comparison of the characteristicsof the individual Pb-free coats as shown in Tables 14 to 16 wereobtained. TABLE 14 Evaluation coats Composition Names (Remainder: Sn)Note Sn-Ag Ag 3.0-5.0% Sn-Bi Bi 1.0-3.0% Sn-special Bi 0.1-0.5% Sn coatfor surface waveform plating mount As-special Pb 5.0-15.0% Solder coat(As waveform plating bathed) for surface mount BF-special Pb 5.0-15.0%Solder coat (boron waveform plating fluoride bathed) for surface mountGlossy solder Pb 5.0-15.0% Ordinary glossy solder plated coat (coat forconnector or the like) Glossless solder Pb 5.0-15.0% Ordinary glosslesssolder plated coat (outer solder coat)

[0124] TABLE 15 Evaluation method Evaluation items Contents AppearanceFree of spot, stain and discoloration Heat resistance heat resistance at150° C. × 3 Hr, no expansion, peeling, discoloration and fall-offSolderability 230° C. × 3 sec × once after heat resistance. Soldershould be 95% or more after soaking Bending 180° C. after heatresistance. No plating separation in bend-back test Melt test No coatoffset when non-heat- resisted product is heated at 270° C. × 30 min andcooled and condensed Peeling Cut a sample after heat resistance with acutter, apply a cellophane tape and remove it, and plating should not bepeeled

[0125] TABLE 16 Evaluation method Evaluation items Contents MeltingMeasured temperature at end of point (° C.) melting using METTLER FP900thermo system Solder Measured five times under the wettability followingconditions using zero- cross time, wet strength measuring conditions,solder checker (SAT- 2000) Sn 605, Pb 40%, TEMP 230° C., PEED 25 mm/sec,DEPTH 2 mm flux present “zero-cross (sec) wet strength (mg)” samplesbefore and after heat resistance n = 5 Vickers hardness Mesurednon-heat-resisted samples under the following conditions by using asuper light load minute hardness meter (model mvk-l). load: 0.5 gf, loadkeeping time: 15 sec, load speed: 0.01 mm. Measured the diagonal line ofa dent three times and computed the Vickers hardness from the averagedent area Bonding strength Sampled ten samples at a width of 3 (kg) mm.Place cut samples one on another with a clearance of 0.3 mm andsolder-dip them under the following conditions using a solder checker.sn 60%, Pb 40%, EMP 230° C., SPEED 25 mm/sec. DEPTH 2 mm. Flux present.Measured force to separation using a push-pull gauge. Samples before andafter heat resistance n = 3 Plating thickness Measured with afluorescent X-ray (μm) film thickness measuring unit Composition %Pb-less plating . . . Measured by SEM Pb-less So (Scaning ElectronMicroscope). N = 3 So plating . . . Measured with a fluorescent X-rayfilm thickness measuring unit. N = 5

EXAMPLES

[0126] Examples of this invention will now be described with referenceto the accompanying drawings. In the diagrams, “1” is a lead frame wherea mount component, such as an IC chip, is mounted, and which has anisland portion 2 in the center portion and a plurality of outer leads atthe periphery.

[0127] “3” denotes outer leads which become to-be-plated portions andprotrude outward of the IC package, and “4” is a ball lead portion whichbecomes a to-be-plated portion as external leads of CSP.

[0128] While alloy plating to be applied to the aforementionedto-be-plated portions contains Sn and a plating material other thanlead, and the composition is as follows. The set ratios are Bi=1.0% withrespect to Sn=99.0% in the first example, and Bi=2.0 to 10.0% withrespect to Sn=98.0 to 90.0% in the second example. The ratio is set toAg=1.0 to 3.0% with respect to Sn=99.0 to 97.0% in the third example.The ratio is set to Ag=3.0 to 5.0% with respect to Sn=97.0 to 95.0% inthe fourth example. The ratio is set to Ag=8.0 to 10.0% with respect toSn=92.0 to 90.0% in the fifth example. The ratio is set to Cu=0.5 to1.0% with respect to Sn=99.5 to 90.0% in the sixth example.

[0129] “5” is an IC chip, a mount component, to be mounted on the leadframe 1, “5′” is an LSI chip, and “5″” is a chip tantalum capacitor. “6”denotes inner leads, and “7” is a package which has the IC chip 5 or theLSI chip 5′ molded with a resin. FIG. 8 shows an IC wafer.

[0130] In FIG. 6, “8” is an IC wafer in a pretreatment in the ICfabrication process, and a plurality of patterns are formed on the ICwafer of 150 to 200 mm in diameter.

SPECIFIC EXAMPLES OF STEPS

[0131] (1) IC Fabrication Process

[0132] a. IC wafer step=form a plurality of patterns on the IC wafer(FIG. 6) of 150 to 200 mm in diameter. There are actually over 300 stepsto this step.

[0133] b. Dicing=dice the IC wafer 8 into individual semiconductor ICchips 5 (FIG. 6). The above are pretreatments.

[0134] c. Die bonding=adhere and fix the IC chip 5 to the island portion1′ of the lead frame 1 (FIG. 7).

[0135] d. Wire bonding=bond the IC chip 5 to electrodes 3′ of the leadframe 1 and the inner leads 6 (FIG. 7).

[0136] e. Resin mold=perform resin molding to form and protect thepackage 7 (FIG. 8). The above are post-treatments.

[0137] (2) IC Assembling Step

[0138] a. IC lead frame forming=form the elongated lead frame 1 by presspunching and photoetching a rolled thin metal plate (42 alloy, copperalloy) (chain-line portion in FIG. 6).

[0139] b. Inner plating=apply gold plating or silver plating to the IClead frame (island portion 2 and inner leads 6) before resin molding(FIG. 6).

[0140] c. Die bonding and wire bonding=bond the IC chip 5 to the islandportion 2 of the lead frame. Then, connect the IC chip 5 to theelectrodes 3′ of the lead frame 1 by the inner leads 6 (FIG. 7).

[0141] d. Resin molding=Seal and fix the IC chip 5 and the inner leads 6in the package 7 with plastic, such as epoxy resin or silicon resin(FIG. 8).

[0142] e. Baking=perform a high-temperature treatment for stabilizationafter resin molding.

[0143] f. Resin variable removal=remove a thin resin coat sticking outover the lead frame 1 at the time of resin molding. Thereafter, performhoning with water jet, resin or glass beads.

[0144] g. Outer plating=Plate the outer leads 3 with a Pb-free materialaccording to this invention containing Sn as an essential component andBi, Ag or Cu by using an electrolytic process with a special waveformwith a melting point in a range of 220 to 250° C. That is, as theaforementioned alloy plating material, Bi is set to or less 1.0% withrespect to Sn=99.0% in the first example, Bi is set to 2.0 to 10.0% withrespect to Sn=98.0 to 90.0% in the second example, Ag is set to 1.0 to3.0% with respect to Sn=99.0 to 97.0% in the third example, Ag is set to3.0 to 5.0% with respect to Sn=97.0 to 95.0% in the fourth example, Agis set to 8.0 to 10.0% with respect to Sn=92.0 to 90.0% in the fifthexample, and Cu is set to 0.5 to 1.0% with respect to Sn=99.5 to 90.0%in the sixth example.

[0145] h. Cutting=cut away the individual IC packages 7 from the linkedframes (chain lines K in FIG. 8, chain lines K in FIG. 5).

[0146] i. Bend the outer leads 3 according to the intended mounting(FIG. 2 shows mounting on a printed circuit board).

[0147] j. Mount the IC package 7 on an electrode pattern 10 of a printedcircuit board 9 and solder bonding portions to the outer leads 3 (FIGS.2 and 3).

[0148] In this case, it is placed on the electrode pattern 10 of theprinted circuit board 9 that faces the ball leads 4 of BGA or CSP (FIG.4).

EFFECT OF THE INVENTION

[0149] With the above-described structure, this invention eliminates Pbfrom a solder material as a bonding material which is essential forelectronic components in the production of electronic devices, therebypreventing a possible pollution problem such that when electronicdevices which become unnecessary are disposed of, Pb leaks and seepsinto groundwater.

[0150] In mounting electronic components, alloy plating equivalent to orgreater than Pb can be acquired without using Pb but by using otherbonding materials than Pb.

BRIEF DESCRIPTION OF THE DRAWINGS

[0151]FIG. 1

[0152]FIG. 1 is a plan view of one piece of a frame 1.

[0153]FIG. 2

[0154]FIG. 2 is a perspective view of an IC package that packages an ICchip to which alloy plating is applied with a substitute bondingmaterial for Pb according to this invention is mounted on a lead frame.

[0155]FIG. 3

[0156]FIG. 3 is a cross-sectional view of an IC package to which alloyplating is applied with a substitute bonding material for Pb accordingto this invention and which is mounted on a printed circuit board.

[0157]FIG. 4

[0158]FIG. 4 is a cross-sectional view of an LSI package to which alloyplating is applied with a substitute bonding material for Pb accordingto this invention and which is mounted on a printed circuit board.

[0159]FIG. 5

[0160]FIG. 5 is a plan view of a chip tantalum capacitor mounted on alead frame.

[0161]FIG. 6

[0162]FIG. 6 is a perspective view of dicing and die bonding in the ICfabrication process.

[0163]FIG. 7

[0164]FIG. 7 is a perspective view of wire bonding in the IC fabricationprocess.

[0165]FIG. 8

[0166]FIG. 8 is a perspective view of packaging a lead frame with resinmolding.

DESCRIPTION OF REFERENCE NUMERALS

[0167] A first measuring portion

[0168] B second measuring portion

[0169] a third measuring portion

[0170] b fourth measuring portion

[0171] 1 lead frame

[0172] 2 island portion

[0173] 3 outer leads

[0174] 4 ball lead portion

[0175] 5 IC chip

[0176] 6 inner leads

[0177] 7 IC package

[0178] 8 IC wafer

[0179] 9 printed circuit board

[0180] 10 electrode pattern

[0181] 11 soldering bonding portion

What is claimed is:
 1. A process for functional alloy plating usingsubstitute bonding material for Pb, comprising applying functional alloyplating to an electronic component to be mounted using an electrolyticprocess with a pulse waveform, said functional alloy plating comprisingSn as base, and Ag, wherein said Ag content to said Sn is set to one of1.0 to 3.0%, 3.0 to 5.0%, and 8.0 to 10.0%.
 2. The process according toclaim 1 wherein the pulse waveform cycles between positive and negative.3. The process according to claim 2 wherein the pulse waveform cyclingbetween positive and negative comprises a 6-phase half-wave.
 4. Theprocess according to claim 3 wherein the 6-phase half wave comprises athyristor 6-phase half wave.
 5. The process according to claim 1 whereinsaid Ag content to said Sn is set to 1.0 to 3.0%.
 6. The processaccording to claim 1 wherein said Ag content to said Sn is set to 3.0 to5.0%.
 7. The process according to claim 1 wherein said Ag content tosaid Sn is set to 8.0 to 10.0%.
 8. A process for functional alloyplating using substitute bonding material for Pb, said processcomprising wire-bonding an IC chip to a lead frame, and subjecting outerleads exposed outside a molded IC package to an electrolytic processwith an Sn content which is 99.0 to 97.0%, and an Ag content to said Snbeing set to 1.0 to 3.0% and with a pulse waveform.
 9. The processaccording to claim 8 wherein the pulse waveform cycles between positiveand negative.
 10. The process according to claim 9 wherein the pulsewaveform cycling between positive and negative comprises a 6-phasehalf-wave.
 11. The process according to claim 10 wherein the 6-phasehalf wave comprises a thyristor 6-phase half wave.
 12. A process forfunctional alloy plating using substitute bonding material for Pb, saidprocess comprising wire-bonding an IC chip to a lead frame, andsubjecting outer leads exposed outside a molded IC package to anelectrolytic process with an Sn content which is 97.0 to 95.0%, and anAg content to said Sn being set to 3.0 to 5.0% and with a pulsewaveform.
 13. The process according to claim 12 wherein the pulsewaveform cycles between positive and negative.
 14. The process accordingto claim 13 wherein the pulse waveform cycling between positive andnegative comprises a 6-phase half-wave.
 15. The process according toclaim 14 wherein the 6-phase half wave comprises a thyristor 6-phasehalf wave.
 16. A process for functional alloy plating using substitutebonding material for Pb, said process comprising wire-bonding an IC chipto a lead frame, and subjecting outer leads exposed outside a molded ICpackage to an electrolytic process with an Sn content which is 92.0 to90.0%, and an Ag content to said Sn being set to 8.0 to 10.0% and with apulse waveform.
 17. The process according to claim 16 wherein the pulsewaveform cycles between positive and negative.
 18. The process accordingto claim 17 wherein the pulse waveform cycling between positive andnegative comprises a 6-phase half-wave.
 19. The process according toclaim 18 wherein the 6-phase half wave comprises a thyristor 6-phasehalf wave.
 20. A process for functional alloy plating using substitutebonding material for Pb comprising subjecting an electrode pattern of aprinted circuit board to an electrolytic process with an Sn contentwhich is 99.0 to 97.0%, and an Ag content to said Sn being set to 1.0 to3.0% and with a pulse waveform.
 21. The process according to claim 20wherein the pulse waveform cycles between positive and negative.
 22. Theprocess according to claim 21 wherein the pulse waveform cycling betweenpositive and negative comprises a 6-phase half-wave.
 23. The processaccording to claim 22 wherein the 6-phase half wave comprises athyristor 6-phase half wave.
 24. A process for functional alloy platingusing substitute bonding material for Pb comprising subjecting anelectrode pattern of a printed circuit board to an electrolytic processwith an Sn content which is 97.0 to 95.0%, and an Ag content to said Snbeing set to 3.0 to 5.0% and with a pulse waveform.
 25. The processaccording to claim 24 wherein the pulse waveform cycles between positiveand negative.
 26. The process according to claim 25 wherein the pulsewaveform cycling between positive and negative comprises a 6-phasehalf-wave.
 27. The process according to claim 26 wherein the 6-phasehalf wave comprises a thyristor 6-phase half wave.
 28. A process forfunctional alloy plating using substitute bonding material for Pbcomprising subjecting an electrode pattern of a printed circuit board toan electrolytic process with an Sn content which is 92.0 to 90.0%, andan Ag content to said Sn being set to 8.0 to 10.0% and with a pulsewaveform.
 29. The process according to claim 28 wherein the pulsewaveform cycles between positive and negative.
 30. The process accordingto claim 29 wherein the pulse waveform cycling between positive andnegative comprises a 6-phase half-wave.
 31. The process according toclaim 30 wherein the 6-phase half wave comprises a thyristor 6-phasehalf wave.
 32. A process for functional alloy plating using substitutebonding material for Pb comprising wire-bonding a chip tantalumcapacitor to a lead frame, and subjecting outer leads exposed outsidesaid chip tantalum capacitor to an electrolytic process with an Sncontent which is 99.0 to 97.0%, and an Ag content to said Sn being setto 1.0 to 3.0% and with a pulse waveform.
 33. The process according toclaim 32 wherein the pulse waveform cycles between positive andnegative.
 34. The process according to claim 33 wherein the pulsewaveform cycling between positive and negative comprises a 6-phasehalf-wave.
 35. The process according to claim 34 wherein the 6-phasehalf wave comprises a thyristor 6-phase half wave.
 36. A process forfunctional alloy plating using substitute bonding material for Pbcomprising wire-bonding a chip tantalum capacitor to a lead frame, andsubjecting outer leads exposed outside said chip tantalum capacitor toan electrolytic process with an Sn content which is 97.0 to 95.0%, andan Ag content to said Sn being set to 3.0 to 5.0% and with a pulsewaveform.
 37. The process according to claim 36 wherein the pulsewaveform cycles between positive and negative.
 38. The process accordingto claim 37 wherein the pulse waveform cycling between positive andnegative comprises a 6-phase half-wave.
 39. The process according toclaim 38 wherein the 6-phase half wave comprises a thyristor 6-phasehalf wave.
 40. A process for functional alloy plating using substitutebonding material for Pb comprising wire-bonding a chip tantalumcapacitor to a lead frame, and subjecting outer leads exposed outsidesaid chip tantalum capacitor to an electrolytic process with an Sncontent which is 92.0 to 90.0%, and afi Ag content to said Sn being setto 8.0 to 10.0% and with a pulse waveform.
 41. The process according toclaim 40 wherein the pulse waveform cycles between positive andnegative.
 42. The process according to claim 41 wherein the pulsewaveform cycling between positive and negative comprises a 6-phasehalf-wave.
 43. The process according to claim 42 wherein the 6-phasehalf wave comprises a thyristor 6-phase half wave.
 44. A process forfunctional alloy plating using substitute bonding material for Pbcomprising subjecting general electronic device component materialsincluding a component material which needs plating for bonding and ageneral component material which needs plating as a functional componentto an electrolytic process with an Sn content which is 99.0 to 97.0%,and an Ag content to said Sn being set to 1.0 to 3.0% and with a pulsewaveforn.
 45. The process according to claim 44 wherein the pulsewaveform cycles between positive and negative.
 46. The process accordingto claim 45 wherein the pulse waveform cycling between positive andnegative comprises a 6-phase half-wave.
 47. The process according toclaim 46 wherein the 6-phase half wave comprises a thyristor 6-phasehalf wave.
 48. A process for functional alloy plating using substitutebonding material for Pb comprising subjecting general electronic devicecomponent materials including a component material which needs platingfor bonding and a general component material which needs plating as afunctional component to an electrolytic process with an Sn content whichis 97.0 to 95.0%, and an Ag content to said Sn being set to 3.0 to 5.0%and with a pulse waveform.
 49. The process according to claim 48 whereinthe pulse waveform cycles between positive and negative.
 50. The processaccording to claim 49 wherein the pulse waveform cycling betweenpositive and negative comprises a 6-phase half-wave.
 51. The processaccording to claim 50 wherein the 6-phase half wave comprises athyristor 6-phase half wave.
 52. A process for functional alloy platingusing substitute bonding material for Pb comprising subjecting generalelectronic device component materials including a component materialwhich needs plating for bonding and a general component material whichneeds plating as a functional component to an electrolytic process withan Sn content which is 92.0 to 90.0%, and an Ag content to said Sn beingset to 8.0 to 10.0% and with a pulse waveform.
 53. The process accordingto claim 52 wherein the pulse waveform cycles between positive andnegative.
 54. The process according to claim 53 wherein the pulsewaveform cycling between positive and negative comprises a 6-phasehalf-wave.
 55. The process according to claim 54 wherein the 6-phasehalf wave comprises a thyristor 6-phase half wave.